A Standard-Cell Placement Tool for Designs with High Row Utilization
نویسندگان
چکیده
In this paper we study the correlation between wirelength and routability for standard-cell placement problem, under the modern place-androute environment. We present a placement tool named Dragon (version 2.1), and show its ability to produce good quality placement for designs with high row utilization. Compared to an industrial placer and an academic state-of-the-art placer, Dragon can produce placement with better routability and shorter total wirelength. We describe many novel algorithmic details and implementation details of this placement tool. Experimental results show that minimizing wirelength improves routability and layout quality.
منابع مشابه
A Standard-Cell Placement Tool for Designs with High Row Utilization
In this paper we study the correlation between wirelength and routability for standard-cell placement problem, under the fixed-die place-androute environment. We present a placement tool with better routability for designs with high row utilization. Compared to a well-known industrial placement tool, our placer produces placements with equal or better routability, 13.2% better half-perimeter wi...
متن کاملAn Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques
In recent years, size of VLSI circuits is dramatically grown and layout generation of current circuits has become a dominant task in design flow. Standard cell placement is an effective stage of physical design and quality of placement affects directly on the performance, power consumption and signal immunity of design. Placement can be performed analytically or heuristically. Analytical placer...
متن کاملA Parallel Row - Based Algorithm with Error Control for Standard - Cell Placement on a Hypercube Multiprocessor
A ncw row-bas& panllcl algorithm for standard-ccll placement targeted for execution on a hypercube multiprocessor is prescntcd. Key fcatures of this implementation include a dynamic simulated-annealing schcdule, row-partitioning of the VLSI chip image, and two novel new approaches to controlling error in parallel ccll-placemcnt algorithms: Heuristic Cell-Coloring and Adaptive (Parallel Move) Se...
متن کاملCongestion Driven ' Placement for ' VLSI Standard Cell Design
The submicron regime has caused the interconnect delay to become a critical determiner of circuit performance. As a result, circuit placement is starting to play an important role in today's high performance chip designs. In addition to wirelength optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming anothe...
متن کاملFlow-Based White Space Allocation for Fixed-Die Standard Cell Placement
Routability is one of the most critical metrics to evaluate the quality of standard cell placement In xed die place ment white space can be used to alleviate congestion and achieve better routability In this paper we propose a new global approach to white space allocation problem for xed die placement and an e ective algorithm to allocate white space according to congestion distribution The pro...
متن کامل